• VLSI DESIGN OF LOW POWER CRYPTOSYSTEM WITH MODIFIED LOPEZ–DAHAB KEY GENERATION ARCHITECTURE

Abstract

Sensitive data transfer between different nodes should be kept secret & secure. The communication system which requires sensitive data transfer uses secured cryptographic algorithms to convert the data into an unrecognizable format. With the intention of increasing the speed and to reduce the hardware complexity, this proposed system focuses on the VLSI implementation of light weight security algorithm such as Tiny Encryption Algorithm (TEA) with MLD.VLSI design of  TEA is to adapt with many real time constraints such as memory, high throughput and low delay. Modified Lopez Dahab (MLD) Key Generation Architecture is the main  additive feature of this proposed system .The proposed system focused on the  Modified Lopez–Dahab key generation architecture for low power applications. To achieve the maximum architectural and timing improvements, we reorganize and reorder the critical path of the Lopez–Dahab scalar point multiplication architecture. The proposed system achieved 2Mb/sec of throughput while compared with conventional throughput of 0.8Mb/sec and also the proposed system consumed 11.123ns of delay with efficient power consumption of 52mwatts.